1.40 (Z01-0001A040) - 0131167:
1. Update - (ITS:0131167) What's the current "ph randomization" setting in the BIOS.
1.40 (Z01-0001A040):
1. Update - Include the following CVE pathces:
IB18410113
IB18410120
IB18410143
IB18410144
IB18410145
IB18410147
IB18410148
IB18410151
IB17040078
IB09480103
1.39 (Z01-0001A039):
1. Fix - (ITS:0090984) Set SMBIOS Type 0 offset 8 writable.
2. Update - (ITS:0090984) Set all SATA port hotplug enabled.
1.38 (Z01-0001A038):
1. Add - (ITS:0090713) Support enabling secure boot by H2OEZE.
1.37 (Z01-0001A037):
1. Add - (ITS:0090638) Boot order available in UEFI binary.
2. Fix - Do not show the menu that H2OEZE does not support.
3. Update - (ITS 0089267) Custom BIOS - ALC233 disable hotplug detect.
1. Add subsystem ID in verb table.
1.36 (Z01-0001A036):
1. Add - (ITS:0085417) Disable EFI Shell by default.
1.35 (Z01-0001A035):
1. Update - (ITS:0083096) Make speed configuration options for all PEG ports visible in BIOS.
1.34 (Z01-0001A034):
1. Update - (ITS:0081398)
1. Change default I219 MAC address to FF:FF:FF:FF:FF:FF.
2. Set BIOS master access to not write Gbe region.
1.33 (Z01-0001A033):
1. Fix - (ITS:0079716) There is no screen during POST with AMT remote desktop when there is no physical monitor attached.
1.32 (Z01-0001A032):
1. Fix - (ITS:0079567) Automatic Failover on PXE boot requires manual intervention.
1.31 (Z01-0001A031):
1. Update - (ITS:0067955) Update CSME to 12.0.64.1551.
2. Fix - (ITS:0067956) RS-485 Tx enable logic doesn't function correctly.
1.30 (Z01-0001A030):
1. (ITS:0064413) Update CSME to 12.0.49.1534.
1.29 (Z01-0002A027):
1. Add default password function.
2. BIOS Version is set to: Z01-0002A027
3. USB Boot is set to: Disabled
1.28 (Z01-0001A027):
1. Update chipset code from 05.23.04.0032 to 05.23.04.0041:
Reference Code Version
CannonLakeSiliconPkg RC 7.0.68.40
AC Module Version
Boot Guard 4351 QS
BIOS Guard 0.9.0
TXT 1.5.0.PV
UEFI Driver Version
GOP 9.0.1091
RAID 17.5.0.1011
LAN (I219) 0.0.23
LAN (I210) 8.7.10
MEBx 12.0.0.0010
Option ROM Version
VBIOS 1020
RAID 17.5.0.1011
PXE (I219) 0.1.13
PXE (I210) 1.5.88
Microcode Version Stepping
m22906ea 00b4 R-0 (Coffee Lake-H)
m02906eb 00ba B-0 (Coffee Lake S 4+2 / Xeon E3 + CNL PCH)
M22906EC 00BE P-0 (Coffee Lake-H)
m22906ed 00be R-0 (Coffee Lake-S + CNL PCH)
Other Version
CSME Corporate 12.0.40.1433v2
1.27 (Z01-0001A026):
1. (ITS:0058906) Implement "Set RTCRST jumper to load BIOS default function".
2. (ITS:0058908)
a. Fix typo in: "Skip Scaning of External Gfx Card", which should be, "Skip Scanning of External Gfx Card".
b. In Device Manager > Primary Video BIOS, remove the option "AGP".
1.26 (Z01-0001A025):
(ITS:0058655)
1. Fix '!' item in PCI Express Root Port menu.
2. Update VCCGT settings:
- Load Line: 2 mOhms
- IMON: 1.07
- Offset 0.149
- Sign: Positive (+)
3. Fix missing 'to' in BIOS entry message ("Press delete to go to")
1.25 (Z01-000023R2):
(ITS:0057244)
1. BIOS Manufacturer changed to: Logic Supply
2. BIOS Model changed to: RXM-181
3. Add splash screen "LogicSupply-BIOS-SplashScreen-1920x1080"
1.24:
1. (ITS:0056865) Add the BIOS Version field, and fill it with an internal LS serial number.
2. (ITS:0056865) Change the default VCCORE and VCCGT AC and DC Loadlines.
1.23:
1. (ITS:0055398) Implementing a Customer Facing BIOS Version.
1.22:
1. (ITS:0056054) Set RTD3 support to disabled by default.
1.21:
1. (ITS:0055059) Update verb table based on "HDACfg-0233-00000000 20190409.txt".
1.20:
1. (ITS:0055232) Add 000000b0 microcode for 906ED CPU.
2. (ITS:0055273) Change PCIE3/PCIE4 from 2x1 to 1x2.
1.19:
1. (ITS:0055234) Change HD audio to UAA mode by default.
2. (ITS:0055059) Update verb table "HDACfg-0233-00000000 20190329.txt".
1.18:
1. (ITS:0055059) Update verb table "HDACfg-0233-00000000 20190325.txt".
1.17:
1. (ITS:0053994) Change default FAN control to CPUFAN.
2. (ITS:0053994) Fix: Set Output Buffer Type to Push-Pull, register is not set.
1.16:
1. (ITS:0053994) Add CPUFANIN/OUT for testing.
1.15:
1. Fix setting wrong "DC Voltage (%)" value when FAN control mode is "Manual".
1.14:
1. (ITS:0053996) View CPU Voltage in BIOS. (Advanced -> SIO NCT5524D -> Hardware Monitor)
2. (ITS:0053994) PWM Fan Control Not Functioning. (Advanced -> SIO NCT5524D -> Fan Control)
1.13:
1. (ITS:0053934) Implement COM port mode selection function.
1.12:
1. (ITS:0053690) Add setup items in SIO configuration page to support select COM port power.
2. (ITS:0053778) Disable DeepSx support in ME.
1.11:
1. Update code base to chipset Tag 05.23.04.0032 and CSME to 12.0.22.1310.
Reference Code Version
CannonLakeSiliconPkg RC 7.0.51.41
AC Module Version
[CoffeeLake]
Boot Guard 4351 QS
BIOS Guard 0.9.0
TXT 1.5.0.PV
UEFI Driver Version
GOP 9.0.1084
RAID 17.0.0.1051
LAN 0.0.19
MEBx 12.0.0.0010
Option ROM Version
VBIOS 1017
RAID 17.0.0.1051
PXE 0.1.13
Microcode Version Stepping
MC0806EA 009E D-0 (Coffee Lake-U43e)
M22906EA 009A U-0 (Coffee Lake-H)
M02906EB 008E B-0 (Coffee Lake-S + CNL PCH)
M22906EC 00A2 P-0 (Coffee Lake-H)
M8060662 0022 C-0 (Cannon Lake-Y22)
M8060663 002A D-0 (Cannon Lake-U GT0 SR18)
MC0806EB 009A W-0 (Whiskey Lake-U42)
1.10:
1. (ITS:0053500) Fix COM ports fail when testing data output using Burn In Test.
1.09:
1. Adjust USB port _PLD/_UPC data to match hardware design.
2. Change Front Page hot key from ESC to DEL and add Boot Manager hot key F10.
3. (ITS:0053385) Add COM port support under Windows.
1.08:
1. (ITS:0052626) Add verb table based on "ALC233_Table_20181213.txt".
1.07:
1. (ITS:0052558)
In "Carbon_0903" schematics, mPCIE slot one connects to PCIE10.
In "Carbon_0925" and "Carbon_1002" schematics, mPCIE slot one connects to PCIE13.
The clock usage policy is set to PCIE10 based on "Carbon_0903" and not changed to PCIE13 based on new version.
Change the policy of clock usage one to PCIE13.
1.06:
1.06-DEBUG:
1. Enable all PCIE ports by default.
2. 1.06 BIOS will output post code to SIO COM1.
1.05-DEBUG:
1. Remove all halt point.
2. Change PlatformImonDisable (FITC setting) from 0 to 1 for testing.
3. Disable RMT log.
4. Output BIOS version if EFI_DEBUG is enabled.
1.04-HALT4:
1. Output "0xF000F030" and halt BIOS after GPIO initial code.
1.04-HALT3:
1. Output "0xF000F020" and halt BIOS before GPIO initial code.
1.04-HALT2:
1. Output "0xF000F010" and halt BIOS before memory initial code.
1.04-HALT1:
1. Output "0xF000F000" and halt BIOS before memory initial code.
1.04-POSTCODE:
1. Send post code to SIO COM1.
1.04:
1. Set GPP_A0 to GPI, not native function 1 for testing.
1.03-RMT3:
1. Disable all PCIE ports for testing.
2. Set back PcdMrcCaVrefConfig to 2.
1.03-RMT2:
1. Change CaVrefConfig from 2 to 0.
1.03:
1.03-DEBUG:
1.03-RMT:
1. Remove unnecessary OEM services during bring up phase.
2. Do not report CRB EC to OS.
3. Set PcdMrcDqPinsInterleaved/PcdMrcDqPinsInterleavedControl to TRUE based on hardware design.
4. Change SPD address to 0xA0, 0x00, 0xA2, 0x00
5. Disable Channel 0 Dimm 1 and Channel 1 Dimm 1 based on hardware design.
6. RMT build to get more log. (1.03-RMT)
1.02:
1. Set the following GPIOs:
COM1_PWR_EN = 0
COM2_PWR_EN = 0
COM1_MODE_0 = 0 (Set in 1.01 BIOS)
COM1_MODE_1 = 0 (Set in 1.01 BIOS)
COM1_MODE_2 = 1 (Set in 1.01 BIOS)
COM2_MODE_0 = 0
COM2_MODE_1 = 0
COM2_MODE_2 = 1
1.01:
Carbon_1.01_X64.bin MD5: 22a59a7b41f66af2b7ef84c0149c4505
1. Power on BIOS (change PCIE clock usage, USB OC pin, GPIOs, ME settings based on hardware design.)